Semiconductor memory devices that are used for storing data can generally be categorized as being either volatile or non-volatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are widely used in situations where power is not always available, is frequently interrupted, or when low power usage is required, such as in mobile telecommunication systems, memory cards for storing music and/or image data, and in other applications.
Generally, cell transistors in non-volatile memory devices have a stacked gate structure. The stacked gate structure includes, sequentially stacked on a channel region of the cell transistor, a gate insulating layer, a floating gate, an inter-gate dielectric layer and a control gate electrode. Viewed in cross section of FIG. 2, some types of non-volatile memory devices have layers of Silicon (in which the channel region is formed), Oxide (which forms the tunneling layer), Nitride (used for the charge trapping layer), Oxide (used for the blocking layer), and Silicon (used for the control gate electrode). Sometimes these layers are collectively referred to as SONOS.
FIGS. 1–4 show the conventional structure of a semiconductor nonvolatile memory device having the SONOS structure that is able to be programmed by hot electron injection. The conventional method of fabricating it will be explained with reference to those figures.
As shown in FIG. 1, a silicon oxide layer for providing a tunneling layer 1 is formed over the entire surface of a semiconductor substrate 6. Next, a silicon nitride layer for providing a charge trapping layer 2 is formed over the whole surface of the tunneling layer 1 by, for example, a chemical vapor deposition (CVD) process. This silicon nitride layer is subjected to a thermal oxidation to form a silicon oxide layer for providing a blocking layer 3. Of course, other methods of forming the blocking layer 3 are known, and can be used instead of or in conjunction with thermal oxidation.
After this, a polycrystalline silicon layer for providing a control gate electrode 4 is formed over the whole surface of the blocking layer 3 by, e.g., a chemical vapor deposition process. The preceding processes make a structure as shown in FIG. 1.
A patterned photoresist (not shown) is then formed on the polycrystalline silicon layer. The patterned photoresist is used as an etching mask to sequentially etch the polycrystalline silicon layer, the blocking layer 3, the charge trapping layer 2 and the tunneling layer 1 in order to create therefrom a memory cell 5 including a polysilicon control gate electrode 14, a blocking layer 13, a charge trapping layer 12 and a tunneling layer 8, as shown in FIG. 2. The photoresist that was used as the etching mask is thereafter removed.
The tunneling layer 8 is a dielectric layer through which charge carriers (holes or electrons) can be injected. The charge trapping layer 12 is a dielectric layer whose function is to trap electrons or holes that were injected through the tunneling layer 8. The function of the blocking layer 13 is to block injected electrons or holes from traveling through to the control gate electrode 14, during writing and erasing operations of the memory cell.
Next, high-concentration diffused regions 15, 17 are formed by implanting a first conductivity type ions into the region of the semiconductor substrate 6 at prescribed portions thereof, self-aligned with opposite sides of the polysilicon control gate 14. The high-concentration diffused regions 15, 17 operate as the source or drain of the memory cell 5, as described below.
The operation of the conventional semiconductor nonvolatile memory device 5 having the SONOS structure will be explained with reference to FIGS. 3 and 4.
When the control gate 14 is positively charged and the diffused regions 15, 17 are properly biased, hot electrons from the semiconductor substrate 6 are trapped into a charge trapping region 7 of the charge trapping layer 12. This is known as writing to or “programming” the memory cell 5. As can be seen in FIG. 3, the trapping region 7 has a length “A”.
Similarly, when the control gate 14 is negatively charged, and the diffused regions 15, 17 are properly biased, holes from the semiconductor substrate 6 can also be trapped in the trapping region 7, combining with any extra electrons that are already in the trapping region. This is known as “erasing” the programmed memory cell 5.
Specifically, the electrons or holes trapped in the trapping region 7 can change the threshold voltage of the semiconductor nonvolatile memory device 5. Typically, programming stops when a threshold voltage of the memory device 5 has reached a certain predetermined point (i.e., when the channel current is reduced to a sufficiently low level). This point is chosen to ensure that a ‘0’ bit stored in the memory device can be distinguished from a ‘1’ bit, and that a certain data retention time has been achieved.
Erasing typically stops when the threshold voltage has reached its former condition (i.e., when enough holes are trapped in the trapping region 7 to recombine with the previously trapped electrons). However, when an excessive amount of electrons are trapped in the trapping region 7 of the charge trapping layer 12, or not enough holes can be injected into the trapping region to bring the memory cell to its former condition, then the threshold voltage of the memory cell 5 cannot be completely erased, i.e., cannot reach the necessary prescribed condition. The memory cell 5 in this state is useless, because it can never be erased.
FIG. 4 shows a sub-portion B of the trapping region 7, along with the sub-portion A. The length labeled A in FIGS. 3 and 4 indicates the area in the trapping region 7 where the electrons are trapped in the charge trapping layer 12, while a length labeled B indicates the portion of the trapping region 7 that traps the holes.
The difference in length of measurements A and B in FIG. 4 may explain the above condition where too many electrons or not enough holes are trapped in the region 7, preventing the memory cell 5 from being completely erased, and thus rendered useless. The fact that electrons are trapped in an area far away from the highly doped area 17 (functioning as the drain or source) may adversely affect the erase operation. In some cases, the memory device 5 cannot be completely erased because the trapping region 7 is programmed too wide. Thus, storing too many electrons or holes in the trapping region 7 and the stored carriers' location relative to the diffused regions 15, 17 can cause errors during operation of the nonvolatile memory device 5.
Embodiments of the invention address these and other deficiencies in the prior art.